Attempts to use CNTs as a via material for LSI interconnects have recently been activated. CNTs perform ballistic conduction, and therefore can be used as an ultralow resistance material that is to be utilized in place of existing metal materials.
To form a CNT via, a contact groove is formed using a standard LSI process, and then CNTs are embedded into the groove by, for example, chemical vapor deposition (CVD). Subsequently, to remove the part of the CNTs formed in an extra field other than the groove, this part is impregnated with an SiO2 film and then fixed by a spin-on-glass (SOG) film. After that, the CNTs are polished by a chemical mechanical polishing (CMP) planarizing treatment, thereby separating vias. After that, a metal film serving as an upper interconnect is formed to complete a multilayer interconnect structure.
In the above method, CMP is performed to make the CNT film and the SOG film have the same polishing rate. Therefore, not only the surfaces of CNT vias, but also alignment marks for performing lithography alignment on the upper layer interconnect, are inevitably flattened.
When processing the metal film on the upper interconnect by lithography, the alignment marks cannot be seen from the outside because the metal film is also provided on the flattened marks to block the light reflected from the marks. Accordingly, accurate lithography alignment between the CNT vias and the upper interconnect cannot be performed and hence significant misalignment may well occur. This is a serious problem in a leading device structure for which microfabrication is required.